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Getting Started with the UPduino FPGA

FPGA Header

An upcoming project is going to require the use of a number of logic gates from the 7400 series of integrated circuits. The project is low speed but it will require a fairly large number of gates.

Could an FPGA provide a suitable proving ground for the project?

This blog has occasionally covered FPGA development boards and simulation software and the free model foundry. The simulation posts used VHDL and commercial simulation software.

But that was over 10 years ago now. Time to revisit the subject.

UPduino 3

The UPduino 3is a small FPGA development board based upon the Lattice UltraPlus ICE40UP5K FPGA. It is a low cost board and looks ideal for starting with FPGA development.

The software stack for development is the open source APIO toolset and a Visual Studio Code extension available.

Step 1 – Remove Installed Software

The first step in getting started was to remove any previously installed software, namely an old version of APIO and icarus-verilog.

pip uninstall apio
brew uninstall icarus-verilog

Step 2 – Install Visual Studio Code Extension

Instructions for installing the APIO extension can be found in the Installing the APIO IDE documentation.

Step 3 – Check the Installation

Executing the command

apio -h

should result in the following output:

Usage: apio [OPTIONS] COMMAND [ARGS]...

  WORK WITH FPGAs WITH EASE.

  Apio is an easy to use and open-source command-line suite designed to
  streamline FPGA programming. It supports a wide range of tasks,
  including linting, building, simulation, unit testing, and programming
  FPGA boards.
.
.
.

Looks like we have the software installed.

Next Up

Simulating some code.

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Saturday, December 27th, 2025 at 1:33 pm • FPGARSS 2.0 feed • leave a response or trackback

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