NE555 Variable Speed Clock

February 9th, 2020 • Electronics, Home Built CPUComments Off on NE555 Variable Speed Clock

The first post about the NE555 presented the theory of operation of the NE555 using an astable clock circuit. This circuit is the basis of a simple low frequency (by todays standards) digital clock or PWM circuit. A clock can be used to synchronise the various components in a digit circuit and PWM is useful in circuits for such things as light (LED) brightness.

This post will look at how the circuit in the first post can be modified to provide a variable clock for a digital circuit. A variable clock can prove useful when debugging a digital circuit.

Basic Astable Circuit

A simple astable circuit looks something like the following:

Astable Logical Layout

Astable Logical Layout

The two resistors R1, R2 and the capacitor control the timing and characteristics of the pulses seen on the output pin of the NE555.

Timing Calculations

The timing calculations given in the data sheet for the NE555 are as follows.

Note that in the following calculations, resistance is expressed on Ohms, capacitance in Farads and time in seconds.

Charge Time

The charge time depends upon the capacitor and the two resistors R1 and R2 as current flows through the two resistors to charge the capacitor. The time taken to charge is given as:

tcharge = 0.693 * (R1 + R2) * C

Discharge Time

The discharge time is only dependent upon the capacitor and R2 as current does not flow through R1 when the circuit is discharging. The time take to discharge is given as:

tdischarge = 0.693 * R2 * C


The period is the sum of the two timings tcharge and tdischarge. This can be expressed as:

Period = 0.693 * (R1 + (2 * R2)) * C


The frequency of a signal is defined as 1/Period. The period of a signal from an astable NE555 is:

Frequency = 1.44 / ((R1 + 2 * R2) * C)

Duty Cycle

The duty cycle of a signal is the percentage of time the signal is high compared to the period of the signal. Thus the duty cycle is given by the following formula:

Duty Cycle (%) = 100 * (R1 + R2) / (R1 + 2 * R2)

Fixed Clock

A fixed clock can be set up easily by changing one or more of the two resistors R1, R2 or the capacitor and a simple spreadsheet will allow you to calculate the circuit characteristics. Doing this allows for the creation of a low (by modern standards) frequency clock quickly and cheaply.

Variable Clock

A variable clock can be useful in debugging digital circuits. The ability to slow the speed of the system can allow the system to be probed easily while maintaining the ability to run the circuit using a free running clock.

As with a fixed clock, the clock characteristics can be changed by varying the value of one or more of R1, R2 or the capacitor.

Variable capacitors and resistors are both available but variable resistors (potentiometers) are more readily available to the hobbyist and so we will follow this option.

This gives two options, changing R1 or R2. Looking at the calculations above it is clear that R2 has the most impact on virtually every operating characteristic of the NE555 and is the only one that can influence the discharge time.

Looking at the tdischarge formula:

tdischarge = 0.693 * R2 * C

the discharge time could theoretically be reduced to zero if R2was allowed to approach 0 Ohms. This can be prevented by replacing R2 with a combination of a fixed value resistor and a potentiometer. The fixed resistor provides for a lower limit for the discharge time of the capacitor.

A quick spreadsheet shows how the circuit will behave as R2 and C are varied:

NE555 Calculations

NE555 Calculations

From the results above it looks like a minimum value for R2 of 1 KOhm and a maximum of 100 KOhm would give a reasonable frequency for a low speed clock.


Lowering the value of R2 1 KOhm and adding a 100 KOhm potentiometer results in the following schematic:

Schematic for a variable speed clock using the NE555 timer

Variable Speed Clock Schematic

The value of the fixed resistor and the potentiometer gives a range of 1 KOhm to 101 KOhm. The additional 1 KOhm of resistance should not impact the frequency too much when the potentiometer is set to its maximum resistance as the calculation is dominated by the 100 KOhm potentiometer.

So that is the theory, how does this work in practice?

Potentiometer Set to 0 Ohms

If we set the potentiometer to 0 Ohms then according to the calculations above, the frequency should be about 48 KHz. The output on the oscilloscope is:

Oscilloscope output when potentiometer set to 0 Ohm

Potentiometer set to 0 Ohm

Potentiometer Set to 100 KOhms

Changing the potentiometer to 100 KOhms we should get a frequency of 712 Hz. The output on the oscilloscope is:

Oscilloscope output when potentiometer set to 100 KOhm

Oscilloscope output when potentiometer set to 100 KOhm

And Somewhere in the Middle

By slowly changing the resistance of the potentiometer we can achieve a steady slow clock of approximately 1 kHz:

NE555 generating a 1 KHz signal

NE555 generating a 1 KHz signal


Clocks provide the heartbeat of most digital circuits, computers certainly require a regular pulse to synchronise the various components in the circuit. The NE555 provides a simple way to generate a variable clock albeit at low frequencies.

The output on the oscilloscope varies from the ideal values given by the calculations. This can be explained by the variations in the tolerances of the various components in the circuits and from the capacitance of the breadboard itself.

NE555 Power on Reset

January 20th, 2020 • ElectronicsComments Off on NE555 Power on Reset

It is essential that when a computer (or any other electrical device) starts, that it starts in a known good state. For a computer, this is accomplished with a power on reset circuit. This circuit is responsible for holding the various reset signals in a known state for a defined period of time when power is applied. Some computers also utilise a reset switch to manually trigger this same reset process.

This post will look at a simple reset circuit from the 1980s using the NE555 timer.


The circuit under consideration should perform the tasks:

  1. Provide two reset signals, one high (Reset) and one low (Reset).
  2. Hold the reset lines in a known state when power is applied.
  3. Provide a manual reset facility.

All of the above can be achieved using a modified monostable NE555 circuit.


The modified schematic for the monostable circuit looks like this:

NE555 Reset Circuit Schematic

NE555 Reset Circuit Schematic

The basic theory of this circuit is that a low pulse on the trigger pin generates a single shot pulse on the output pin of the NE555.

The resistor and capacitor in the right-hand part of the circuit form a standard monostable configuration. This circuit is taken from the NE555 datasheet. Using the formula in the datasheet, the period of the stable, high pulse on the output is given by the formula:

Period = 1.1 * R * C

Using the values in the circuit, R = 47K and C = 10uF. Plugging these values into the equation we find that the period of the stable pulse is 0.517 seconds.

The inverter provided by the 74LS04 allows for the generation of both a high and a low (Reset and Reset) signals from the circuit.

The resistor and capacitor on the left hand side of the circuit debounce the switch connected to the trigger of the circuit. They also hold the trigger under the 1.67V threshold for a short period of time following startup. This provides the power on reset element of the circuit.

This circuit can also be viewed using the logical layout discussed in the previous aricle on the theory of operation:

NE555 Logical Layout

NE555 Logical Layout


Putting the above circuit together on breadboard gives something like the following:

NE555 Reset Circuit on Breadboard

NE555 Reset Circuit on Breadboard


In the following, all images from the oscilloscope will show the NE555 output in yellow and where present, the signal on the trigger pin will be in blue.

At startup, it is expected that there should be a short (500ms approx) signal on the output pin of the NE555.

NE555 Power on Reset Oscilloscope Output

NE555 Power on Reset Oscilloscope Output

So far, so good. The next requirement is to allow the user to manually reset the system. This is done using the switch connected to the trigger pin on the NE555. Pressing the button shows the following on the oscilloscope:

NE555 Reset Circuit Short Button Press

NE555 Reset Circuit Short Button Press

The short press on the button generates the required reset pulse on the output pin of the NE555.

The datasheet for the NE555 warns against holding the trigger pin low for a period of time longer than the duration of the output pulse. So in this case, the trigger pin should not be held low for longer than 517ms. This could be a problem as it is easy to exceed this period in normal use. So what happens if the trigger pin is held low for an extended period of time? Changing the scale on the oscilloscope to 250ms per division and we see the following:

NE555 Reset Circuit Multiple Button Presses on Oscilloscope

NE555 Reset Circuit Multiple Button Presses on Oscilloscope

The leftmost pulse is the result of a short press of the button. As expected, the output of the NE555 goes high for 517ms.

The middle pulse shows what happens when the button is pressed and held for an extended period of time. In this case, the button was pressed for about 2s. As you can see, the reset pulse remains high for the duration of the button press and then returns low.

The rightmost pulse shows what happens when the switch is pressed once more for a short period. As you can see, the NE555 returns to its normal mode of operation and generates a 517ms pulse.


The NE555 really does deserve it’s reputation as a versatile chip. This simple circuit provides a digital circuit with the ability to start in a known state by providing a reset pulse when power is applied to the system. It also provides a mechanism for resetting a system on demand using a switch connected to the trigger pin.

And now for a piece of history, circuits such as this appeared in many of the early 8-bit computers from the 1980s.

NE555 Theory of Operation

July 17th, 2019 • Electronics, Home Built CPUComments Off on NE555 Theory of Operation

Oscilloscope Trace

Oscilloscope Trace

Ohhhh no, not another post about the NE555 timer! I’m sorry to say, yes, this is another article (or two) about the NE555, how it works and some applications.

I blog for two main reasons:

  • As an aide-memoire
  • Hopefully others will find these posts useful

So this first post will cover the theory behind the operation of the NE555 using the astable circuit as an example.

Logical Layout of the NE555

The NE555 has four logical units and they can be viewed logically in the following layout:

Logical units with NE555

NE555 Logical Layout

These logical units are:

  1. Resistor ladder
  2. Two comparators
  3. S-R latch
  4. Discharge circuit

These components allow the engineering of a wide number of circuits using this versatile chip. This series of articles will cover four applications:

  • Astable circuit (a.k.a a clock)
  • Reset circuit
  • Button debouncing a push switch
  • Button debouncing with selection (i.e. latching switch)

Let’s start with looking at the four logical components identified above.

Resistor Ladder

Resistor Ladder

Resistor Ladder

The resistor ladder in the original chip used 5K resistors. The use of three equal value resistors supply 1/3 * Vcc and 2/3 * Vcc to the two comparators.




The two comparators compare two of the input voltages to the two values from the resistor ladder, namely, 1/3 * Vcc and 2/3 * Vcc. They output a high value if the voltage on the positive input is greater than the voltage on the negative input.

The top comparator has the negative input connected to 2/3 * Vcc and the positive input connected to the threshold pin. This comparator will out a high value when the threshold is greater than 2/3 * Vcc and a low value at all other times.

The lower comparator has the negative input connected to 1/3 * Vcc and the positive input connected to the trigger input. This comparator will output a high value when the trigger is less than 1/3 * Vcc and a low value at all other times.

S-R Latch

S-R Latch

S-R Latch

The S-R latch uses the output from the two comparators to determine if the output of the NE555 should be turned on or off. The inverted output from the latch (Q) is connected to the output pin of the NE555 through an invertor.

Q is also connected to the base of the transistor connected to the discharge pin.

Discharge Circuit

Discharge Circuit

Discharge Circuit

The discharge pin is connected to ground through a transistor. The base of the transistor is connected to the inverted output of the S-R latch. So the discharge pin is connected to ground when the S-R latch is in the reset state.

So How Does it Work?

An astable circuit can be used to understand how the various components of the NE555 work together and it is this circuit we will examine next.

Astable Circuit

One of the circuits that can be constructed using the NE555 is a low frequency PWM circuit, known in NE555 parlance as an astable circuit. This can be used in a wide variety of applications from flashing LEDs to the provision of a low frequency clock signal for a digital circuit.

An simple astable circuit can be constructed using two resistors, a capacitor and the NE555 chip. Using the above logical diagram as a starting point we would connect the additional components as follows:

Astable Logical Layout

Astable Logical Layout

The reset pin should be connected to Vcc and the control pin should be connected to ground through a 100nF or 10nF capacitor.

The operation of the astable circuit will be consider by progressing through time from the point that power is applied to the circuit. It is assumed that Vcc is equal to 5V. The makes the nominal values for 1/3 * Vcc = 1.67V and 2/3 * Vcc = 3.3V.

Power On

Capacitor starts to charge

Capacitor starts to charge

At the point where the chip starts the resistor network inside the NE555 will split Vcc into two as noted above. These will appear on the two comparators negative (for comparator 1) and positive (for comparator 2) inputs.

At the same time, the capacitor C will be charged through resistors R1 and R2. At the point shortly after power up there will be very little charge on the capacitor, for argument, let us say that this is 0V. This will place 0V on both the trigger and threshold pins of the NE555.

Comparator 1 will compare the voltage on the trigger pin (negative input) to 1.67V (positive input). As 0V is less than 1.67V this will result in a high output from comparator 1. This high output is applied to the set pin of the S-R latch. Following this through, this will turn the Q output on and the inverted Q output off.

Q output drives both base of the transistor connected to the discharge pin, turning the transistor off and the output pin through the invertor, turning the output on.

Comparator 2 is comparing positive input connected to the charge on the capacitor (currently 0V) to 3.3V. Following this through as we did with comparator 1, 0V is not grester than 3.3V and so comparator 2 outputs a low signal. The low signal on the reset input in the S-R latch has no effect on the output from the S-R latch.

So shortly after power on, comparator 1 has turned the output of the NE555 on and capacitor C is charging. The various parts of the circuit have the inputs and outputs set to the values in the diagram above marked in red.

Capacitor Charge Reaches 1.67V

As time progresses, the charge on the capacitor will reach and then exceed 1.67V. The circuit will look like the following:

Capacitor continues to charge

Capacitor continues to charge

At this point a change will occur to comparator 1. The negative input voltage (from the trigger pin) will reach 1.67V. The voltage on the negative input to the comparator will no longer be greater than 1.67V and so the output of the comparator will change from high (on) to low (off). The low signal applied to the set input of the S-R latch will have no effect on the S-R latch (both set and reset inputs to the S-R latch are now low and so the previous state is remembered).

At this point there is no change to the output of the circuit, the output is still latched on and charge continues to build up on the capacitor.

Capacitor Charge Reaches 3.33V

Eventually the charge on the capacitor will reach and exceed 3.33V. This will change the circuit to the following state:

Capacitor starts to discharge

Capacitor starts to discharge

There will be no change to the output of comparator 1 as the voltage applied to the negative input of the comparator remains greater than 1.67V just as it was in the above stage.

The main change is triggered by comparator 2. The charge on the capacitor is applied to the positive input to the comparator which is now greater than or equal to the 3.33V (from the resistor ladder) applied to the negative input. This causes the comparator to set the output high.

A high output on comparator 2 is applied to the reset input of the S-R latch. This turns the set output (Q) of the latch off and the inverted output (Q) on.

Two things happen when Q is turned on:

  1. The output of the NE555 is turned off
  2. The transistor connected to the discharge pin is turned on

Turning the transistor on changes the flow of current through the circuit. So far current has been flowing through the two resistors, R1 and R2 to charge the capacitor, C. Now the current starts to flow from Vcc to ground through R1.

Current will now also start to flow from the capacitor, through R2 and the transistor to ground. At some point the charge on the capacitor will drop below 3.33V. This will be reflected on the threshold pin connected to comparator 2 and the output of this comparator will be turned off:

Middle of Capacitor Discharging

Middle of Capacitor Discharging

The output of the S-R latch will continue to hold the last state until and hence the output remains off until a signal is applied to the set pin of the S-R latch and so current continues to flow through the transistor.

Capacitor Charge Drops Below 1.67V

At some point the charge on the capacitor will drop below 1.67V and comparator 1 turns on and so Q is turned off once more. The circuit starts to behave as though the system has just been powered on with one slight difference, the charge on the capacitor C starts at 1.67V instead of 0V. The whole cycle of charging and discharging repeats continuously.

Circuit Output

Building the circuit on breadboard and then connecting up an oscilloscope to the discharge and output pin shows the following trace:

Oscilloscope Trace

Oscilloscope Trace

The output is shown in yellow and the discharge is shown in blue.

It is clear to see the charging and discharging of the capacitor coincides with the change in the output state of the NE555.

Timing Calculations

The timing calculations given in the data sheet for the NE555 are as follows.

Note that in the following calculations, resistance is expressed on Ohms, capacitance in Farads and time in seconds.

Charge Time

The charge time depends upon the capacitor and the two resistors R1 and R2 as current flows through the two resistors to charge the capacitor. The time taken to charge is given as:

tcharge = 0.693 * (R1 + R2) * C

Discharge Time

The discharge time is only dependent upon the capacitor and R2 as current does not flow through R1 when the circuit is discharging. the time take to discharge is given as:

tdischarge = 0.693 * R2 * C


The period is the sum of the two timings tcharge and tdischarge. This can be expressed as:

Period = = 0.693 * (R1 + (2 * R2)) * C

The duty cycle and frequency are easily derived from the above.

And Finally…

The NE555 is a versatile chip that can act as more than a simple oscillator. The principles of the above circuit can be used in clock generation, switch debouncing, reset circuits and a whole range of other applications, several of which will be covered in following articles.

Dave Jones (EEVBlog) has put together the Three Fives Timer Kit and has videoed the build process and also provided a run down of the theory of operation referring to the kit schematic. Key times in the video are:

  • 0 – 36 Minutes: Building the kit
  • 36 – 54 Minutes: Examination of the schematic and run through the theory of operation
  • 54 – 62 Minutes: Checking the voltages and output from the kit using an astable circuit

Netduino.Foundation – Device Drivers for Netduino

February 10th, 2018 • Electronics, NetduinoComments Off on Netduino.Foundation – Device Drivers for Netduino
Netduino Foundation Banner

Netduino Foundation Banner

It has been a very busy few months both in and out of work as evidenced by the silence here. The last few months has seen a fair amount to time spent working with the Netduino boards developing documentation and libraries.

I was given a Nedtuino board in 2010 as a present and I have never looked back. The orignal Netduino Plus was upgraded to the Netduino Plus 2, the Netduino WiFi and numerous electronics projects have come about all due to that original present.

The attraction of the Netduino is the fact that you can work in C# with Visual Studio. Another big selling point is Visual Studio and the powerful debugging features available to the developer.

In summary, it’s a great prototyping and test environment. If I ever have a problem and want to test a theory quickly I always fall back to these boards.


One difficulty with Netduino was it was sometimes difficult to find drivers for sensors, displays etc. Support for devices relied upon community members having written a driver and making the source available. In fairness, many community members did just that.

Wilderness Labs have recently taken ownership of the Netduino brand and technology. A new approach has brought some innovations:

  • Support for Visual Studio for Mac
  • New community forum
  • Developer documentation for the Netduino
  • Electronics tutorials
  • Netduino.Foundtion collection of drivers and core functionality
  • Source code is available on GitHub
  • Nuget support

It is still possible to use the Netduino without using Netduino.Foundtion but the library makes a number of tasks easier and quicker.

As well as a number of core peripherals there is support for a library of drivers covering a variety of devices:

Device Description
74595 Shift Registers Everyones favourite output expander
DS323x Real time clock
Graphics Library General purpose graphics library
LCD MicroLiquidCrystal library for 16×2 and 20×4 LCD displays
Serial LCD Serial LCD backpack
SSD1306 OLED Display (128×32 and 128×64)
BME280 Temperature, pressure and humidity
HIH6130 Temperature and humidity
MPL115A2 Temperature and pressure
MPL3115A2 Temperature and pressue
SHT31D Temperature and humidity
SI7021 Temperature and humidity
TMP102 Temperature
ALS-PT19 Analog light sensor
TSL2561 Infra-red compensated light sensor
ADXL335 Triple axis accelerometer (+/- 3g)
ADXL345 Triple axis accelerometer (+/- 16g)
MAG3110 Triple axis magnetometer
PIR Motion detection
Servo Generic servo library
Analog Temperature Analog temperature sensors such as LM35/36/37 etc.

All of the drivers are supplied with source code, sample applications and comprehensive documentation.


It is great to see the Netduino with a new supporter. The new documentation and libraries make the platform easier to use.

Arithmetic Logic Unit Chip Selection

July 16th, 2017 • Electronics, Home Built CPUComments Off on Arithmetic Logic Unit Chip Selection

In the previous post, a high level design for an Arithmetic Logic Unit (ALU) was presented. It is time to consider how this could be implemented.

7400 Series Integrated Circuits

The 7400 series of integrated circuits became a staple in computer design and digital electronics in the 1970s and 1980s. These packages implemented everything from simple logic gates (AND, OR, XOR, NOR etc.) through to complex functions such as Error Detection and Correction (see 742960). See this article for a comprehensive list of chips and their functions.

So popular were these chips that they are still available today in the original DIL (Dual In-line Package) as well as surface mount packages.

A number of variations of these ICs were produced:

Series Description
74 Standard TTL
74LS Low-power Schottky
74LAS Advanced Schottky
74ALS Advanced Low-power Schottky

The above list is not comprehensive and many more variations are available.

This series of posts will concentrate on using the LS series of chips where possible.

Internals of the ALU

The ALU in the SSEM needs to support addition (for the JRP instruction) and subtraction (for the SUB and LDN instructions). The previous post presented the internal view of the ALU for the SSEM as:

ALU Internals

Internal view of an Arithmetic Logic Unit showing the control signals and data paths.

The ALU has five distinct components:

  1. Storage for the A and B operands (registers)
  2. Zero Unit
  3. XOR
  4. Adder
  5. ALU Output

Let’s look at how each of these could possibly be implemented using 74LS00 series integrated circuits.

Storage for the A and B operands (registers)

Both of the operands are connected to the data bus at the same time:

Operand A and B

Operand A and B

The Load control signal determines when the input signals should be stored in the register. Each of the registers holding the operand has an independent load signal. So for this part of the ALU a component is required that will:

  1. Take the value on the input pins and store the value
  2. Only load the data into the register when the trigger signal has a known value
  3. Present the stored value on the output pins

The above requirement fits the description of a Flip-Flop (also known as a Latch).

The 74LS00 series has a number of flip-flops and latches available. The 74LS373 contains an octal transparent latch with three state output. This chip is still commonly available and has the following properties:

  1. Input signals can be latched (stored) in the internal registers on request
  2. The output from the latch can be turned on or off, again, on request

The above functions are controlled by two signals:

  1. Clock
  2. Output Enable (~OE)


When the clock signal is low the inputs are effectively disconnected from the latches. the latches will therefore remain unchanged and hold the previously latched value.

A high clock signal will allow the input pins to the connected to the latches. Any changes on the inputs are presented to the latches. This holds true for as long as the clock signal is in the high state.

The state of the input pins is held in the latches when the clock signal transitions from high to low (on the falling edge of the clock).

Output Enable

The output enable pin is an active low pin (denoted here by the ~ symbol before the name of the pin). This means that the contents of the latches will be output from the chip when the ~OE pin is in the low state.

Putting the ~OE pin in a high state disconnects the latches from the output pins and puts the outputs in a high impedance (also known as a high-Z) state.

Setting ~OE low while the clock pin is high means that the outputs will follow the inputs. This happens because the high clock signal allows the inputs to be connected to the latches and the low output signal puts the value in the latches on to the output pins.

Loading the Latch

From the above description, the Clock pin should be connected to the Load A and Load B signals of the respective operands. This will allow the latch to be loaded with the input signals when the load signal falls from high to low.

The inputs to the chips should be connected to the data bus directly and simultaneously. Data cannot be loaded into the latch until the appropriate load signal transitions from high to low. The load signals will control when the operand changes as follows:

  • Load A (or Load B) signals are low then the inputs will have no impact on the operands. The outputs will reflect the previous value stored in the latch.
  • When Load A (or Load B) is high then the contents of the data bus will be presented to the respective latch. The output of the respective operand will reflect the current contents of the data bus.
  • When the Load A (or Load B) signal falls from high to low, the current contents of the data bus will be stored in the respective operand. The output will reflect this value no matter what happens on the data bus.

Aside: in 2013, the intention was to simulate the SSEM in VHDL. The 74HC373 was simulated in a series of posts around that time.


The next block available is the 74LS series is the XOR block:

Operand B and XOR

Operand B and XOR

This block performs one part of the negation process allowing the adder to also perform subtraction. The XOR truth table is:

~Add/Subtract Input Value Output
0 0 0
0 1 1
1 0 1
1 1 0

In twos complement, the first part of generating a negative number is to invert the bits in the original number. If you examine the above truth table, when the ~Add/Subtract signal is low, the output reflects the input value. When ~Add/Subtract is high then the output is the inverse of the input value.

~Add/Subtract Operation
0 Add
1 Subtract

So, setting the ~Add/Subtract signal high when the ALU is subtracting operand B from operand A and low when the ALU is adding operand A to operand B will ensure that the correct value is passed through to the adder.

The 74LS86 is a quad 2-input XOR gate (contains four 2-input XOR gates) in a single package. The necessary functionality is achieved by connecting the A inputs (not to be confused with the A operand) of each gate to the ~Add/Subtract signal. All of the A inputs are therefore connected together. The B inputs are connected to the outputs of the B operand latch.


The zero unit sits between the output of the A operand and the Adder. Its function is to select between two possible input values:

  1. Zero
  2. A operand

and pass the selection on to the Adder.

Operand A and Zero

Operand A and Zero

A number of possibilities exist:

  • Use the ~OE signal on the A output to simply turn the output off when zero is required. This may require the use of pull down resistors to prevent a floating signal.
  • Use a buffer chip such as the 74LS245 to connect the Adder to ground when ~OE on the A operand goes high

A little investigation is required.


The adder unit takes the inputs and simply adds them together:

Adder with inputs.

Adder with inputs.

The 74LS283 is a four bit full adder with carry in and carry out. An 8-bit adder is created by chaining two four bit adders together:

In the case of subtraction, the final part of the negation of a twos complement number is to add 1 to the inverted bit pattern of the original number. Setting the carry in on the first adder effectively adds one to the number. The same ~Add/Subtract signal in the XOR block can be used here as it is low for addition (zero will be added to the sum) and high for subtraction (one will be added to the sum).

ALU Output

The ALU output takes the output of the adder and makes this available to the data bus:

ALU Output

ALU Output

Output to the data bus is controlled by the ALUOutout signal and this function can be performed by a buffer circuit. The 74LS245 is an octal bus transceiver with non-inverting three state outputs. The direction of signal transmission can be controlled using the DIR pin on this chip. In the case of the ALU, the direction is always from the ALU to the data bus and so this pin can be held high (or low) permanently.

Output from 74LS245 is controlled by the ~OE pin. This is an active low pin and the chip is transparent when the signal is low and in high impedance mode when this pin is held high.


All of the integrated circuits for the high level functionality of the ALU have been identified. The next step is to put this together and see if it works as expected.

Something for the next article.

Arithmetic Logic Unit

June 26th, 2017 • Electronics, Home Built CPUComments Off on Arithmetic Logic Unit

The February post regarding the SSEM presented a software implementation of the core hardware:

  • Program counter a.k.a Current Instruction (CI)
  • Arithmetic Logic Unit (ALU)
  • Instruction register a.k.a Present Instruction (PI)
  • Registers (memory)

So, how easy this would be to implement the ALU in 1970s hardware, namely, 74LS series of chips.

Arithmetic Logic Unit

The only explicit arithmetic operation implemented by the ALU is the SUB instruction. There is however, one other operation that requires an arithmetic operation to be performed, the JRP instruction. This instruction adds the contents of a store line to CI and stores the result in CI. The inclusion of an ADD instruction to the ALU instruction set will support the JRP instruction.

Before we progress further it is worth noting that the SSEM uses twos complement representation to store numbers.

The high level view of the ALU and the way in which it interacts with the other components can be viewed as follows:

High level view of an Arithmetic Logic Unit.

High level view of an Arithmetic Logic Unit.

Two busses run through this CPU:

  1. Data Bus
  2. Control Bus

The Data Bus is used to move data from one part of the CPU to another. This is also connected to the external data bus of the computer allowing the CPU to store and retrieve data from system peripherals and memory.

The Control Bus determines which operations are performed by the CPU (in this particular case, by the ALU) at any point in time.

The ALU uses two input operands (A and B) from the Data Bus. Operations are performed on the two operands, the type of operation is determined by the signals on the Control Bus. The results of the operation are then placed in the ALU Output register. The final step is to make this result available to the Data Bus.

The fact that the SSEM implements only these two arithmetic instructions operating on twos complement numbers leads to a very simple ALU design with very few control signals.

Data Bus

As noted, the data bus moves data around the system. The ALU requires two operands for the ADD or SUB operations. These can be implemented in a single operation or in several stages.

Single Operation

Supplying the data in a single operation would require the data bus to be twice as wide as the word size. In the case of the SSEM this would require a data bus that is 64-bits wide. Operand A would be supplied by one half of the signals on the data bus. Operand B would be supplied by the signals on the other half of the bus.

Multiple Steps

Supplying each operand independently would require a two step process, the first step puts operand A on the data bus and loads into the operand A register. The second step puts operand B on the data bus and loads the data into the operand B register. This is slower, taking two steps, but simplifies the hardware design as a 32-bit data bus is used.

Control Bus

The operation of the CPU is orchestrated by the signals present on the control bus. In the case of the instructions being implemented (ADD and SUB) using two registers the following signals are required:

  1. Load operand A (place the contents on the data bus into operand A)
  2. Load operand B (place the contents on the data bus into operand B)
  3. Output result (place the ALU result onto the data bus)
  4. Add or subtract (Select either addition or subtraction)

There is another instruction that would benefit from having access to the ALU, namely, Load Negative (LDN). This instruction loads a negative number into the accumulator. A negated number can be obtained by subtracting the original number (from a store line) from 0.

If we design the system so that the subtrahend (the number to be subtracted) is always placed in the B operand and operand A can be zero then we can support the LDN instruction. This leads to the final signal, Operand A or Zero.

The full list becomes:

  1. Load operand A (place the contents on the data bus into operand A)
  2. Load operand B (place the contents on the data bus into operand B)
  3. Output result (place the ALU result onto the data bus)
  4. Add or subtract (Select either addition or subtraction)
  5. Operand A or Zero

Inside the ALU

If we add the data paths and control signals to the above diagram we have the following:

ALU Internals

Internal view of an Arithmetic Logic Unit showing the control signals and data paths.

The data paths are shown as broad arrows. The control signals are drawn in red.

Loading the Operand Registers

The data from the data bus is presented to both the A and the B operands at the same time. The data is loaded into the register when the appropriate Load A or Load B signal is set.

Zero Operation

The zero operation is only needed for the A operand. This block will either pass the value in operand A through to the adder (for the SUB, ADD and JRP instruction) or pass 0 through to the adder (for the LDN instruction).


The XOR block is used to help with the negation of the number in the B operand. In twos complement, a negative number is obtained by inverting the bits in the original number and the adding 1. The XOR helps with the inversion process. Consider the truth table for the XOR operator:

Control Signal Input Value Output
0 0 0
0 1 1
1 0 1
1 1 0

Note that when the Control Signal is 0 then the output from the XOR gate reflects the value on the Input Value. When the Control Signal is 1 then the output is the inverse of the Input Value.

This provides a method for solving the first part of the problem of generating the twos complement negative number, namely, inverting all of the bits in the positive number.


The adder does exactly what it’s name suggests, it adds two numbers together. Normally, these units have a carry in and a carry out signal to allow multiple units to be chained together:

Two chained four bit adders.

Two chained four bit adders.

When the ~Add/Subtract control signal is set to 0 then the XOR block passes through operand B unchanged. The carry in signal to the first of the adders (Adder-0) is set to 0. The result is that operand A and operand B are added together. This supports the JRP instruction which requires an addition.

When the ~Add/Subtract control signal is set to 1 then the XOR block inverts the bits in operand B. The additional 1 needed for the twos complement process is provided by passing the ~Add/Subtract control signal to the carry in input to the first adder unit (Adder-0 in the above diagram).

Result Output

The final part of the problem is to control when the result from the calculation is output on to the data bus.


A lot of theory, next step is to consider how this can be put into practice.

Something for the next article.

Design the System

April 14th, 2017 • Electronics, Software Development2 Comments »

One of the current projects on the go is a level shifter for the Teensy 3.6 using the TXS0108E chip. The aim is to allow the use of as many of the Teensy’s GPIO pins as possible to allow the development of another project that is working on 5V logic levels.

This project reminded me that when putting together a microcontroller project that the system is made up of both hardware and software. Sometimes a design decision made in one element can have an adverse effect on the other.

Design Decisions

From the start it was decided that the GPIO pins would have a one to one mapping from the microcontroller to the external bus. So pin 1 on the microcontroller would map to pin 1 on the external connectors.

This would make coding easy when using the Arduino API. So connecting to the external bus and outputting a digital high signal on pin 1 would become:

pinMode(1, OUTPUT);
digitalWrite(1, HIGH);


Putting the circuit together in KiCAD resulted in the following design:

PCB Layout

PCB Layout

TXS0108E Schematic

TXS0108E Schematic

As you can see, the Teensy GPIOS (TIO-1…) mapped directly to the external bus (GPIO-1…)

When translated into the rats nest there were three occurrences of the following:

PCB Layout

PCB Layout

Routing this was going to be a nightmare.

Changing the Design

At this point the penny dropped that a small change in the software would make the routing a whole lot easier.

Instead of using the pin numbers directly, a #define could be used for the external bus pin numbers. The above snippet would become:

#define BUS_IO1    30
pinMode(BUS_IO1, OUTPUT);
digitalWrite(BUS_IO1, HIGH);

This small change to the design created a one off task to create a header file for the board but it made the routing a lot easier.


Sometimes a small change may create a new task (creating the header file) but may possibly save more time elsewhere in the project.

Moral of the story, Design the system as a whole, not the individual components.

March Musings

March 31st, 2017 • ElectronicsComments Off on March Musings

March has been a funny old month. The launch of the Raspbery Pi Zero W was an interesting event. Most of February was spent evaluating the direction of future developments. The launch of the Pi Zero W in early March influenced those decisions.

It feels like nothing was really completed but the foundations for the next few months have been set. Here’s a few of the things March has bought our way:

  • Release of the Raspberry Pi Zero W
  • Moving from MicroPython on the ESP32 to Python on the Pi
  • TXS0108E level shifting IC
  • PlatformIO
  • Teensy 3.6


More precisely, MicroPython. The increasing number of platforms supporting MicroPython has made this an interesting development environment. In theory the code developed on one microcontroller supporting MicroPython should be portable to other microcontrollers with relative ease.

The Raspberry Pi Zero W changed all of that.

There were several microcontrollers running MicroPython at the start of February, the ESP8266 was common and cheaply available. A beta version of MicroPython became available for the more capable ESP32 around the same time.

The arrival of the Zero W means that the full Python language is available on a development board running 5-20 times faster than an equivalent microcontroller development board. All this with the added bonus of WiFi and SD card built in.

Another attractive feature of the Zero W is the cost in the UK. The most powerful microcontroller boards available in the UK cost between 1.5-2 times that of the Zero W including shipping.

The net result, I’m starting to look at the Pi Zero W as a possible go to board for future projects.

Level Shifting

One recent project requires the use of 5V logic, a problem when current microcontroller boards are using 3.3V logic levels. Some are 5V tolerant, but not all. Ideally the microcontroller I am after should allow for 40+ GPIO pins. The only microcontroller in the arsenal with this number of pins is the Teensy 3.6. Sadly this in only tolerant to 3.3V signals. Interestingly, I found a reasonably priced bidirectional level shifter, the TXS0108E, so some experimenting required to see if I can use this part. The aim is to use the Teensy to inject test signals.

Time to break out the breadboards and KiCAD.


I have had PlatformIO installed on the laptop since I first came across it last year. For most of that time it was being used as a simple text editor. What I never appreciated was the ability to program a number of development boards, a large number of development boards.

Time to uninstall the Arduino IDE on the Mac.

A current project requires some memory, only a small amount, something suited to the 2114 4096-bit memory IC. A quick eBay search results in 20 ICs in the post. Only problem now is to make sure I understand how they work and test the batch of chip. Enter the Arduino Uno and PlatformIO.

Teensy 3.6

As noted, one current project requires a large number of IOs, something the Teensy 3.6 can bring. A quick package update installs the Teensy 3.6 board into the PlatformIO environment.

Time to write and deploy a quick test application, enter Blinky… No luck. PlatformIO uses the teensy_loader_cli application to deploy the hex file to the Teensy board. The default package deployed with PlatformIO did not upload the binary file to the Teensy. the solution was to build a new version of the teensy_loader_cli application and overwrite the one supplied with PlatformIO. Success!

For those who are interested, the solution is:

  • Download the source code from GitHub
  • Edit the Makefile
  • Change the OS version to MacOS
  • Uncomment the line USE_LIBUSB ?= YES
  • Rebuild the application
  • Copy the new version of the application to the tools directory, in my case this was ~/.platformio/packages/tool-teensy


It seems that nothing much was completed but the work set the stage for future developments.

Manchester Baby (SSEM) Emulator

February 12th, 2017 • Electronics, Software DevelopmentComments Off on Manchester Baby (SSEM) Emulator

The Manchester Small Scale Experimental Machine (SSEM) or Manchester Baby as it became known, was the first computer capable of executing a stored program. The Baby was meant as a proving ground for the early computer technology having only 32 words of memory and a small instruction set.

A replica of the original Manchester Baby is currently on show in the Museum of Science and Industry in Castlefield, Manchester.

Manchester Baby at MOSI

Manchester Baby at Museum of Science and Industry August 2012.

As you can see, it is a large machine weighing in at over 1 ton (that’s imperial, not metric, hence the spelling).

Manchester Baby Architecture

A full breakdown on the Manchester Baby’s architecture can be found in the Wikipedia article above as well as several PDFs, all of which can be found online. The following is meant as a brief overview to present some background to the Python code that will be discussed later.

Storage Lines

Baby used 32-bit words with numbers represented in twos complement form. The words were stored in store lines with the least significant bit (LSB) first (to the left of the word). This is the reverse of most modern computer architectures where the LSB is held in the right most position.

The storage lines are equivalent to memory in modern computers. Each storage line contains a 32-bit value and the value could represent an instruction or data. When used as an instruction, the storage line is interpreted as follows:

Bits Description
0-5 Storage line number to be operated on
6-12 Not used
13-15 Opcode
16-31 Not used

As already noted, when the storage line is interpreted as data then the storage line contains a 32-bit number stored in twos complement form with the LSB to the left and the most significant bit (MSB) to the right.

This mixing of data and program in the same memory is known as von Neumann architecture named after John von Neumann. For those who are interested, the memory architecture where program and data are stored in separate storage areas is known as a Harvard architecture.

SSEM Instruction Set

Baby used three bits for the instruction opcode, bits 13, 14 and 15 in each 32 bit word. This gave a maximum of 8 possible instructions. In fact, only seven were implemented.

Binary Code Mnemonic Description
000 JMP S Jump to the address obtained from memory address S (absolute jump)
100 JRP S Add the value in store line S to the program counter (relative jump)
010 LDN S Load the accumulator with the negated value in store line S
110 STO S Store the accumulator into store line S
001 or 101 SUB S Subtract the contents of store line S from the accumulator
011 CMP If the accumulator is negative then add 1 to the program counter (i.e. skip the next instruction)
111 STOP Stop the program

When reading the above table it is important to remember that the LSB is to the left.


Baby had three storage areas within the CPU:

  1. Current Instruction (CI)
  2. Present Instruction (PI)
  3. Accumulator

The current instruction is the modern day equivalent of the program counter. This contains the address of the instruction currently executing. CI is incremented before the instruction is fetched from memory. At startup, CI is loaded with the value 0. This means that the first instruction fetched from memory for execution is the instruction in storage line 1.

The present instruction (PI) is the actual instruction that is currently being executed.

As with modern architecture, the accumulator is used as a working store containing the results of any calculations.

Python Emulator

A small Python application has been developed in order to verify my understanding of the architecture of the Manchester Baby. The application is a console application with the following brief:

  1. Read a program from a file and setup the store lines
  2. Display the store lines and registers before the program starts
  3. Execute the program displaying the instructions as they are executed
  4. Display the store lines and registers at the end of the program run

The application was broken down into four distinct parts:

  1. – implement a class containing a value in a register or storage line
  2. – Number of store lines containing the application and data
  3. – Implement the logic of the CPU
  4. – Main program logic, reading a program from file and executing the program

The source code for the above along with several samples and test programs can be fount on Github.

A register is defined as a 32-bit value. The Register class stores the value and has some logic for checking that the value passed does not exceed the value permitted for a 32-bit value. Note that no other checks or interpretation of the value is made.

StoreLines holds a number of Registers, the default when created is 32 registers as this maps on to the number of store lines in the original Manchester Baby. It is possible to have a larger number of store lines.

The CPU class executes the application held in the store lines. It is also responsible for displaying the state of the CPU and the instructions being executed.

The main program file contains an assembler (a very primitive one with little error checking) for the Baby’s instruction set. It allows a file to be read and the store lines setup and finally instructs the CPU to execute the program.

SSEM Assembler Files

The assembler provided in the file is primitive and provides little error checking. It is still useful for loading applications into the store lines ready for execution. The file format is best explained by examining a sample file:

--  Test the Load and subtract functions.
--  At the end of the program execution the accumulator should hold the value 15.
00: NUM 0
01: LDN 20      -- Load accumulator with the contents of line 20 (-A)
02: SUB 21      -- Subtract the contents of line 21 from the accumulator (-A - B)
03: STO 22      -- Store the result in line 22
04: LDN 22      -- Load accumulator (negated) with line 22 (-1 * (-A - B))
05: STOP        -- End of the program.
20: NUM 10      -- A
21: NUM 5       -- B
22: NUM 0       -- Result

Two minus signs indicate an inline comment. Everything following is ignored.

An instruction line has the following form:

Store line number: Instruction Operand

The store line number is the location in the Store that will be used hold the instruction or data.

Instruction is the mnemonic for the instruction. The some of the instructions have synonyms:

Mnemonic Synonyms

As well as instructions a number may also be given using the NUM mnemonic.

All of the mnemonics requiring a store number (all except STOP and CMP) read the Operand field as the store line number. The NUM mnemonic stores the Operand in the store line as is.


Testing the application was going to be tricky without a reference. Part of the reason for developing the Python implementation was to check my understanding of the operation of the SSEM. Luckily, David Sharp has developed an emulator written in Java. I can use this to check the results of the Python code.

The original test program run on the Manchester Baby was a calculation of factors. This was used as it would stress the machine. This same application can be found in several online samples and will be used as the test application. The program is as follows:

--  Tom Kilburns Highest Common Factor for 989
01:   LDN 18
02:   LDN 19
03:   SUB 20
04:   CMP
05:   JRP 21
06:   SUB 22
07:   STO 24
08:   LDN 22
09:   SUB 23
10:   STO 20
11:   LDN 20
12:   STO 22
13:   LDN 24
14:   CMP
15:   JMP 25
16:   JMP 18
17:   STOP
18:   NUM 0
19:   NUM -989
20:   NUM 988
21:   NUM -3
22:   NUM -988
23:   NUM 1
24:   NUM 0
25:   NUM 16

Running on the Java Emulator

Executing the above code in David Sharps emulator gives the following output on the storage tube:

Java Simulator Storage Lines

Result of the HCF application shown on the storage lines of the Java emulator.

and disassembler view:

Storage Lines Disassembled

Result of the program execution disassembled in the Java emulator.

And running on the Python version of the emulator results in the following output in the console:

Python Output

Final output from the Python emulator.

Examination of the output shows that the applications have resulted in the same output. Note that the slight variation in the final output of the Python code is due to the way in which numbers are extracted from the registers. Examination of the bit patterns in the store lines shows that the Java and Python emulators have resulted in the same values.


The Baby presented an ideal way to start to examine computer architecture due to its prmitive nature. The small storage space and simple instruction set allowed emulation in only a few lines of code.

Soak Testing (Minor Update)

October 15th, 2016 • Electronics, ESP8266, Software DevelopmentComments Off on Soak Testing (Minor Update)

The weather station project has been struggling for part of September with a random exception in my code. The source of the exception was finally identified although the exact cause is still a mystery. As a temporary measure, the component and the associated source code were removed from the project, this allowed the project to continue.

Source of the Exception

In the previous post, Define a Minimum Viable Product and Ship it, I discussed a replacement for the clock module. This module was changed from the DS3234 to the DS3231 freeing up four additional pins (the DS3231 is an I2C peripheral and the DS3234 uses SPI). This change seems to have introduced some instability into the system.

Several days debugging followed after which I was still unable to isolate the problem. The interim solution is to remove the module and use the Ticker class to trigger an interrupt. Not ideal but this will allow the rest of the software to be soak tested.

The additional Ticker object fires once per minute to trigger the reading of the sensors. In addition, the interrupt will check the current time and if the hour and minute are both zero then the application will reset the pluviometer counter.

Soak Testing

As mentioned above, one Ticker object is generating an interrupt once per minute. The frequency of the interrupt is higher than will be used in the final project. One minute is more than enough time to perform the sensor readings and log this to the internet but also frequent enough to simulate a prolonged period in the field.

The prototype board was also located close to the final home for the sensors. This hit a problem as the range of the WiFi network was not sufficient for the ESP8266. This problem has prevented the prototype to be tested in the field at the moment.


The prototype board is currently sited on a window ledge in the house. taking temperature, humidity and luminosity readings once per minute. This data is logged to the Sparkfun Phant Data Service. The system has been running continuously for the last 7 days (approximately 10,000 readings).

The software seems stable at the moment, the next problem, extend the range of the WiFi network.