Simulating the 74HC373

In my last post on VHDL, I looked at simulating the 74HC373 using the Free Model Foundry std373 transparent latch component. This component simulated a single transparent latch and allowed the addition of timing information to give a more realistic simulation.

The 74HC373 contains eight of these transparent latches in a single DIP package with a single latch enable and single output enable line. This post builds on the earlier work and simulates the DIP package rather than the single latch.

Test Case

Before we progress we should remind ourselves of the test bench created for the single latch. This changed the data inputs (D, le and oe) to the single latched and verified the output traces against the output expected. The simulated output looked like this:

Simulation With Added Timing Data

Simulation With Added Timing Data

For this example we will use exactly the same sequence of events but use eight data bits rather than just a single bit. The sequence of events should look the same but the data (when present) will reflect the fact that more than one data line is being manipulated.

Implementing the 74HC373

Being new to VHDL and the design process using this language, the final solution took an hour or two to realise. I considered various options but all tended to be code related which is probably natural giving my software development background.

Then inspiration struck and I came up with the following code:

library IEEE;

entity HC74373 is
    port ( dataIn : in  STD_LOGIC_VECTOR (7 downto 0);
           dataOut : out  STD_LOGIC_VECTOR (7 downto 0);
           le : in  STD_LOGIC;
           oe : in  STD_LOGIC);
end HC74373;

architecture Behavioral of HC74373 is
    component std373 is 
            Q : out std_logic;
            D, LE, OENeg : in std_logic
    end component;
    d0: std373 port map (LE => le, OENeg => oe, D => dataIn(0), Q => dataOut(0));
    d1: std373 port map (LE => le, OENeg => oe, D => dataIn(1), Q => dataOut(1));
    d2: std373 port map (LE => le, OENeg => oe, D => dataIn(2), Q => dataOut(2));
    d3: std373 port map (LE => le, OENeg => oe, D => dataIn(3), Q => dataOut(3));
    d4: std373 port map (LE => le, OENeg => oe, D => dataIn(4), Q => dataOut(4));
    d5: std373 port map (LE => le, OENeg => oe, D => dataIn(5), Q => dataOut(5));
    d6: std373 port map (LE => le, OENeg => oe, D => dataIn(6), Q => dataOut(6));
    d7: std373 port map (LE => le, OENeg => oe, D => dataIn(7), Q => dataOut(7));
end Behavioral;

No coding (as in conventional software development). All of the work is performed by the mapping of the ports from the std_logic_vector to the bits std_logic inputs and outputs to the std373 component.


As already mentioned, the sequence of events we will use as a test case will match tests for a single latch. The test bench becomes:

USE ieee.std_logic_1164.ALL;

— Uncomment the following library declaration if using
— arithmetic functions with Signed or Unsigned values
–USE ieee.numeric_std.ALL;

ENTITY HC74373TestBench IS
END HC74373TestBench;

ARCHITECTURE behavior OF HC74373TestBench IS

— Component Declaration for the Unit Under Test (UUT)

dataIn : IN std_logic_vector(7 downto 0);
dataOut : OUT std_logic_vector(7 downto 0);
le : IN std_logic;
oe : IN std_logic

signal dataIn : std_logic_vector(7 downto 0) := (others => ‘0’);
signal le : std_logic := ‘1’;
signal oe : std_logic := ‘1’;

signal dataOut : std_logic_vector(7 downto 0);
signal clock : std_logic := ‘0’;

— Instantiate the Unit Under Test (UUT)
uut: HC74373 PORT MAP
dataIn => dataIn,
dataOut => dataOut,
le => le,
oe => oe

— Clock process definitions
clockProcess: process
clock <= '0'; wait for 125 ns; clock <= '1'; wait for 125 ns; end process; -- Stimulus process stim_proc: process begin -- -- Initial condition, latch should have stabilised and be high impedance. -- wait for 125 ns; -- -- Set data in to all zeroes, output should still be high impedance. -- le <= '0'; wait for 125 ns; -- -- Now enable the output. -- oe <= '0'; wait for 125 ns; -- -- Changing the data whilst LE is low does not change the output. -- dataIn <= "11110000"; wait for 125 ns; -- -- Now set the data in whilst latch and output enable are both allowed. -- Data output should become 11001100. -- le <= '1'; wait for 125 ns; -- -- Now set the data in whilst latch and output enable are both allowed. -- Data output should become 11110000. -- dataIn <= "10101010"; wait for 125 ns; -- -- Turn off the latch enable and set the data in bits. The data output -- should not change. -- le <= '1'; dataIn <= "00110011"; wait for 125 ns; -- -- Re-enable the output, should become 10101010 as 00110011 has not -- been latched yet. -- oe <= '1'; wait for 125 ns; -- -- Output is turned off, latch the data and enable the output. -- le <= '0'; wait for 125 ns; le <= '1'; oe <= '0'; wait for 125 ns; -- -- End of test. -- wait; end process; END; [/code]

The output from the simulator is:

74HC373 Simulation Output

74HC373 Simulation Output

As you can see, the sequence of events for the single latch matches those for the 74HC373 component.


Now I look at this solution it seems obvious. Something to bear in mind as I start to use more and more components from the Free Model Foundry library.

Next stop a buffer driver.

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Thursday, January 2nd, 2014 at 8:16 pm • Electronics, FPGARSS 2.0 feed Both comments and pings are currently closed.

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